mirror of
https://github.com/g4klx/MMDVM.git
synced 2026-10-23 02:55:01 +02:00
Add the LL library files and clean up some indentation.
This commit is contained in:
Jonathan Naylor
+279
-269
@@ -60,47 +60,47 @@ void USART1_IRQHandler()
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void InitUSART1(int speed)
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{
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// USART1 - TXD PA9 - RXD PA10 - pins on mmdvm pi board
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GPIO_InitTypeDef GPIO_InitStructure;
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USART_InitTypeDef USART_InitStructure;
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NVIC_InitTypeDef NVIC_InitStructure;
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// USART1 - TXD PA9 - RXD PA10 - pins on mmdvm pi board
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GPIO_InitTypeDef GPIO_InitStructure;
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USART_InitTypeDef USART_InitStructure;
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NVIC_InitTypeDef NVIC_InitStructure;
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RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOA, ENABLE);
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RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1, ENABLE);
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GPIO_PinAFConfig(GPIOA, GPIO_PinSource9, GPIO_AF_USART1);
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GPIO_PinAFConfig(GPIOA, GPIO_PinSource10, GPIO_AF_USART1);
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RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOA, ENABLE);
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RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1, ENABLE);
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GPIO_PinAFConfig(GPIOA, GPIO_PinSource9, GPIO_AF_USART1);
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GPIO_PinAFConfig(GPIOA, GPIO_PinSource10, GPIO_AF_USART1);
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// USART IRQ init
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NVIC_InitStructure.NVIC_IRQChannel = USART1_IRQn;
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NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
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NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1;
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NVIC_InitStructure.NVIC_IRQChannelSubPriority = 1;
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NVIC_Init(&NVIC_InitStructure);
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// USART IRQ init
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NVIC_InitStructure.NVIC_IRQChannel = USART1_IRQn;
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NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
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NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1;
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NVIC_InitStructure.NVIC_IRQChannelSubPriority = 1;
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NVIC_Init(&NVIC_InitStructure);
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// Configure USART as alternate function
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GPIO_StructInit(&GPIO_InitStructure);
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GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
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GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;
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GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
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GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9 | GPIO_Pin_10; // Tx | Rx
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GPIO_InitStructure.GPIO_Speed = GPIO_Fast_Speed;
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GPIO_Init(GPIOA, &GPIO_InitStructure);
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// Configure USART as alternate function
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GPIO_StructInit(&GPIO_InitStructure);
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GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
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GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;
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GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
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GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9 | GPIO_Pin_10; // Tx | Rx
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GPIO_InitStructure.GPIO_Speed = GPIO_Fast_Speed;
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GPIO_Init(GPIOA, &GPIO_InitStructure);
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// Configure USART baud rate
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USART_StructInit(&USART_InitStructure);
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USART_InitStructure.USART_BaudRate = speed;
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USART_InitStructure.USART_WordLength = USART_WordLength_8b;
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USART_InitStructure.USART_StopBits = USART_StopBits_1;
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USART_InitStructure.USART_Parity = USART_Parity_No;
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USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
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USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
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USART_Init(USART1, &USART_InitStructure);
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// Configure USART baud rate
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USART_StructInit(&USART_InitStructure);
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USART_InitStructure.USART_BaudRate = speed;
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USART_InitStructure.USART_WordLength = USART_WordLength_8b;
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USART_InitStructure.USART_StopBits = USART_StopBits_1;
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USART_InitStructure.USART_Parity = USART_Parity_No;
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USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
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USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
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USART_Init(USART1, &USART_InitStructure);
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USART_Cmd(USART1, ENABLE);
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USART_Cmd(USART1, ENABLE);
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USART_ITConfig(USART1, USART_IT_RXNE, ENABLE);
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USART_ITConfig(USART1, USART_IT_RXNE, ENABLE);
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m_USART1.init(USART1);
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m_USART1.init(USART1);
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}
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#endif
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@@ -113,52 +113,52 @@ static CSTMUART m_USART2;
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void USART2_IRQHandler()
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{
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m_USART2.handleIRQ();
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m_USART2.handleIRQ();
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}
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void InitUSART2(int speed)
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{
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// USART2 - TXD PA2 - RXD PA3
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GPIO_InitTypeDef GPIO_InitStructure;
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USART_InitTypeDef USART_InitStructure;
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NVIC_InitTypeDef NVIC_InitStructure;
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// USART2 - TXD PA2 - RXD PA3
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GPIO_InitTypeDef GPIO_InitStructure;
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USART_InitTypeDef USART_InitStructure;
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NVIC_InitTypeDef NVIC_InitStructure;
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RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOA, ENABLE);
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RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART2, ENABLE);
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GPIO_PinAFConfig(GPIOA, GPIO_PinSource2, GPIO_AF_USART2);
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GPIO_PinAFConfig(GPIOA, GPIO_PinSource3, GPIO_AF_USART2);
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RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOA, ENABLE);
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RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART2, ENABLE);
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GPIO_PinAFConfig(GPIOA, GPIO_PinSource2, GPIO_AF_USART2);
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GPIO_PinAFConfig(GPIOA, GPIO_PinSource3, GPIO_AF_USART2);
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// USART IRQ init
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NVIC_InitStructure.NVIC_IRQChannel = USART2_IRQn;
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NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
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NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1;
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NVIC_InitStructure.NVIC_IRQChannelSubPriority = 1;
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NVIC_Init(&NVIC_InitStructure);
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// USART IRQ init
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NVIC_InitStructure.NVIC_IRQChannel = USART2_IRQn;
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NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
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NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1;
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NVIC_InitStructure.NVIC_IRQChannelSubPriority = 1;
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NVIC_Init(&NVIC_InitStructure);
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// Configure USART as alternate function
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GPIO_StructInit(&GPIO_InitStructure);
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GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
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GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;
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GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
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GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2 | GPIO_Pin_3; // Tx | Rx
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GPIO_InitStructure.GPIO_Speed = GPIO_Fast_Speed;
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GPIO_Init(GPIOA, &GPIO_InitStructure);
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// Configure USART as alternate function
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GPIO_StructInit(&GPIO_InitStructure);
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GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
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GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;
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GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
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GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2 | GPIO_Pin_3; // Tx | Rx
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GPIO_InitStructure.GPIO_Speed = GPIO_Fast_Speed;
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GPIO_Init(GPIOA, &GPIO_InitStructure);
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// Configure USART baud rate
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USART_StructInit(&USART_InitStructure);
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USART_InitStructure.USART_BaudRate = speed;
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USART_InitStructure.USART_WordLength = USART_WordLength_8b;
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USART_InitStructure.USART_StopBits = USART_StopBits_1;
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USART_InitStructure.USART_Parity = USART_Parity_No;
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USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
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USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
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USART_Init(USART2, &USART_InitStructure);
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// Configure USART baud rate
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USART_StructInit(&USART_InitStructure);
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USART_InitStructure.USART_BaudRate = speed;
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USART_InitStructure.USART_WordLength = USART_WordLength_8b;
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USART_InitStructure.USART_StopBits = USART_StopBits_1;
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USART_InitStructure.USART_Parity = USART_Parity_No;
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USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
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USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
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USART_Init(USART2, &USART_InitStructure);
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USART_Cmd(USART2, ENABLE);
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USART_Cmd(USART2, ENABLE);
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USART_ITConfig(USART2, USART_IT_RXNE, ENABLE);
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USART_ITConfig(USART2, USART_IT_RXNE, ENABLE);
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m_USART2.init(USART2);
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m_USART2.init(USART2);
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}
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#endif
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@@ -170,7 +170,7 @@ static CSTMUART m_USART3;
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void USART3_IRQHandler()
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{
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m_USART3.handleIRQ();
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m_USART3.handleIRQ();
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}
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#if defined(STM32F7_NUCLEO)
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@@ -193,46 +193,46 @@ void USART3_IRQHandler()
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void InitUSART3(int speed)
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{
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GPIO_InitTypeDef GPIO_InitStructure;
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USART_InitTypeDef USART_InitStructure;
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NVIC_InitTypeDef NVIC_InitStructure;
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GPIO_InitTypeDef GPIO_InitStructure;
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USART_InitTypeDef USART_InitStructure;
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NVIC_InitTypeDef NVIC_InitStructure;
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RCC_AHB1PeriphClockCmd(USART3_RCC_Periph, ENABLE);
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RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART3, ENABLE);
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GPIO_PinAFConfig(USART3_GPIO_PORT, USART3_GPIO_PinSource_TX, GPIO_AF_USART3);
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GPIO_PinAFConfig(USART3_GPIO_PORT, USART3_GPIO_PinSource_RX, GPIO_AF_USART3);
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RCC_AHB1PeriphClockCmd(USART3_RCC_Periph, ENABLE);
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RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART3, ENABLE);
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GPIO_PinAFConfig(USART3_GPIO_PORT, USART3_GPIO_PinSource_TX, GPIO_AF_USART3);
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GPIO_PinAFConfig(USART3_GPIO_PORT, USART3_GPIO_PinSource_RX, GPIO_AF_USART3);
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// USART IRQ init
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NVIC_InitStructure.NVIC_IRQChannel = USART3_IRQn;
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NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
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NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1;
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NVIC_InitStructure.NVIC_IRQChannelSubPriority = 1;
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NVIC_Init(&NVIC_InitStructure);
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// USART IRQ init
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NVIC_InitStructure.NVIC_IRQChannel = USART3_IRQn;
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NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
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NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1;
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NVIC_InitStructure.NVIC_IRQChannelSubPriority = 1;
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NVIC_Init(&NVIC_InitStructure);
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// Configure USART as alternate function
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GPIO_StructInit(&GPIO_InitStructure);
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GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
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GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;
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GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
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GPIO_InitStructure.GPIO_Pin = USART3_GPIO_Pin_TX | USART3_GPIO_Pin_RX; // Tx | Rx
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GPIO_InitStructure.GPIO_Speed = GPIO_Fast_Speed;
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GPIO_Init(USART3_GPIO_PORT, &GPIO_InitStructure);
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// Configure USART as alternate function
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GPIO_StructInit(&GPIO_InitStructure);
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GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
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GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;
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GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
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GPIO_InitStructure.GPIO_Pin = USART3_GPIO_Pin_TX | USART3_GPIO_Pin_RX; // Tx | Rx
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GPIO_InitStructure.GPIO_Speed = GPIO_Fast_Speed;
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GPIO_Init(USART3_GPIO_PORT, &GPIO_InitStructure);
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// Configure USART baud rate
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USART_StructInit(&USART_InitStructure);
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USART_InitStructure.USART_BaudRate = speed;
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USART_InitStructure.USART_WordLength = USART_WordLength_8b;
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USART_InitStructure.USART_StopBits = USART_StopBits_1;
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USART_InitStructure.USART_Parity = USART_Parity_No;
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USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
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USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
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USART_Init(USART3, &USART_InitStructure);
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// Configure USART baud rate
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USART_StructInit(&USART_InitStructure);
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USART_InitStructure.USART_BaudRate = speed;
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USART_InitStructure.USART_WordLength = USART_WordLength_8b;
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USART_InitStructure.USART_StopBits = USART_StopBits_1;
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USART_InitStructure.USART_Parity = USART_Parity_No;
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USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
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USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
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USART_Init(USART3, &USART_InitStructure);
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USART_Cmd(USART3, ENABLE);
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USART_Cmd(USART3, ENABLE);
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USART_ITConfig(USART3, USART_IT_RXNE, ENABLE);
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USART_ITConfig(USART3, USART_IT_RXNE, ENABLE);
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m_USART3.init(USART3);
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m_USART3.init(USART3);
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}
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#endif
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@@ -244,56 +244,56 @@ static CSTMUART m_UART5;
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void UART5_IRQHandler()
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{
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m_UART5.handleIRQ();
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m_UART5.handleIRQ();
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}
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void InitUART5(int speed)
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{
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// UART5 - TXD PC12 - RXD PD2
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GPIO_InitTypeDef GPIO_InitStructure;
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USART_InitTypeDef USART_InitStructure;
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NVIC_InitTypeDef NVIC_InitStructure;
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// UART5 - TXD PC12 - RXD PD2
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GPIO_InitTypeDef GPIO_InitStructure;
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USART_InitTypeDef USART_InitStructure;
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NVIC_InitTypeDef NVIC_InitStructure;
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RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOC, ENABLE);
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RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOD, ENABLE);
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RCC_APB1PeriphClockCmd(RCC_APB1Periph_UART5, ENABLE);
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GPIO_PinAFConfig(GPIOC, GPIO_PinSource12, GPIO_AF_UART5);
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GPIO_PinAFConfig(GPIOD, GPIO_PinSource2, GPIO_AF_UART5);
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RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOC, ENABLE);
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RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOD, ENABLE);
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RCC_APB1PeriphClockCmd(RCC_APB1Periph_UART5, ENABLE);
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GPIO_PinAFConfig(GPIOC, GPIO_PinSource12, GPIO_AF_UART5);
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GPIO_PinAFConfig(GPIOD, GPIO_PinSource2, GPIO_AF_UART5);
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// USART IRQ init
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NVIC_InitStructure.NVIC_IRQChannel = UART5_IRQn;
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NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
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NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1;
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NVIC_InitStructure.NVIC_IRQChannelSubPriority = 1;
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NVIC_Init(&NVIC_InitStructure);
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// USART IRQ init
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NVIC_InitStructure.NVIC_IRQChannel = UART5_IRQn;
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NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
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NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1;
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NVIC_InitStructure.NVIC_IRQChannelSubPriority = 1;
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NVIC_Init(&NVIC_InitStructure);
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// Configure USART as alternate function
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GPIO_StructInit(&GPIO_InitStructure);
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GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
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GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;
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GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
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GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12; // Tx
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GPIO_InitStructure.GPIO_Speed = GPIO_Fast_Speed;
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GPIO_Init(GPIOC, &GPIO_InitStructure);
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// Configure USART as alternate function
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GPIO_StructInit(&GPIO_InitStructure);
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GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
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GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;
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GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
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GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12; // Tx
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GPIO_InitStructure.GPIO_Speed = GPIO_Fast_Speed;
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GPIO_Init(GPIOC, &GPIO_InitStructure);
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GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2; // Rx
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GPIO_Init(GPIOD, &GPIO_InitStructure);
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GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2; // Rx
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GPIO_Init(GPIOD, &GPIO_InitStructure);
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// Configure USART baud rate
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USART_StructInit(&USART_InitStructure);
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USART_InitStructure.USART_BaudRate = speed;
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USART_InitStructure.USART_WordLength = USART_WordLength_8b;
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USART_InitStructure.USART_StopBits = USART_StopBits_1;
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USART_InitStructure.USART_Parity = USART_Parity_No;
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USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
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USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
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USART_Init(UART5, &USART_InitStructure);
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// Configure USART baud rate
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USART_StructInit(&USART_InitStructure);
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USART_InitStructure.USART_BaudRate = speed;
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USART_InitStructure.USART_WordLength = USART_WordLength_8b;
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USART_InitStructure.USART_StopBits = USART_StopBits_1;
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USART_InitStructure.USART_Parity = USART_Parity_No;
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USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
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USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
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USART_Init(UART5, &USART_InitStructure);
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USART_Cmd(UART5, ENABLE);
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USART_Cmd(UART5, ENABLE);
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USART_ITConfig(UART5, USART_IT_RXNE, ENABLE);
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USART_ITConfig(UART5, USART_IT_RXNE, ENABLE);
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m_UART5.init(UART5);
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m_UART5.init(UART5);
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}
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#endif
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@@ -301,150 +301,160 @@ void InitUART5(int speed)
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void CSerialPort::beginInt(uint8_t n, int speed)
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{
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switch (n) {
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case 1U:
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#if defined(STM32F4_DISCOVERY) || defined(STM32F7_NUCLEO)
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InitUSART3(speed);
|
||||
#elif defined(STM32F4_PI) || defined(STM32F4_F4M) || defined(STM32F722_PI) || defined(STM32F722_F7M) || defined(STM32F722_RPT_HAT) || defined(STM32F4_DVM) || defined(STM32F7_DVM) || defined(STM32F4_EDA_405) || defined(STM32F4_EDA_446)
|
||||
InitUSART1(speed);
|
||||
#elif defined(STM32F4_NUCLEO) || defined(STM32F4_RPT_HAT_TGO)
|
||||
InitUSART2(speed);
|
||||
#elif defined(DRCC_DVM)
|
||||
InitUSART1(speed);
|
||||
#endif
|
||||
break;
|
||||
case 3U:
|
||||
#if defined(STM32F4_NUCLEO) && defined(STM32F4_NUCLEO_ARDUINO_HEADER)
|
||||
InitUSART1(speed);
|
||||
#elif defined(DRCC_DVM)
|
||||
InitUSART2(speed);
|
||||
#else
|
||||
InitUART5(speed);
|
||||
#endif
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
switch (n) {
|
||||
case 1U:
|
||||
#if defined(STM32F4_DISCOVERY) || defined(STM32F7_NUCLEO)
|
||||
InitUSART3(speed);
|
||||
#elif defined(STM32F4_PI) || defined(STM32F4_F4M) || defined(STM32F722_PI) || defined(STM32F722_F7M) || defined(STM32F722_RPT_HAT) || defined(STM32F4_DVM) || defined(STM32F7_DVM) || defined(STM32F4_EDA_405) || defined(STM32F4_EDA_446)
|
||||
InitUSART1(speed);
|
||||
#elif defined(STM32F4_NUCLEO) || defined(STM32F4_RPT_HAT_TGO)
|
||||
InitUSART2(speed);
|
||||
#elif defined(DRCC_DVM)
|
||||
InitUSART1(speed);
|
||||
#endif
|
||||
break;
|
||||
|
||||
case 3U:
|
||||
#if defined(STM32F4_NUCLEO) && defined(STM32F4_NUCLEO_ARDUINO_HEADER)
|
||||
InitUSART1(speed);
|
||||
#elif defined(DRCC_DVM)
|
||||
InitUSART2(speed);
|
||||
#else
|
||||
InitUART5(speed);
|
||||
#endif
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
int CSerialPort::availableForReadInt(uint8_t n)
|
||||
{
|
||||
switch (n) {
|
||||
case 1U:
|
||||
#if defined(STM32F4_DISCOVERY) || defined(STM32F7_NUCLEO)
|
||||
return m_USART3.available();//AvailUSART3();
|
||||
#elif defined(STM32F4_PI) || defined(STM32F4_F4M) || defined(STM32F722_PI) || defined(STM32F722_F7M) || defined(STM32F722_RPT_HAT) || defined(STM32F4_DVM) || defined(STM32F7_DVM) || defined(STM32F4_EDA_405) || defined(STM32F4_EDA_446)
|
||||
return m_USART1.available();//AvailUSART1();
|
||||
#elif defined(STM32F4_NUCLEO) || defined(STM32F4_RPT_HAT_TGO)
|
||||
return m_USART2.available();//AvailUSART2();
|
||||
#elif defined(DRCC_DVM)
|
||||
return m_USART1.available();//AvailUSART1();
|
||||
#endif
|
||||
case 3U:
|
||||
#if defined(STM32F4_NUCLEO) && defined(STM32F4_NUCLEO_ARDUINO_HEADER)
|
||||
return m_USART1.available(); //AvailUSART1();
|
||||
#elif defined(DRCC_DVM)
|
||||
return m_USART2.available(); //AvailUSART2();
|
||||
#else
|
||||
return m_UART5.available();//AvailUART5();
|
||||
#endif
|
||||
default:
|
||||
return 0;
|
||||
}
|
||||
switch (n) {
|
||||
case 1U:
|
||||
#if defined(STM32F4_DISCOVERY) || defined(STM32F7_NUCLEO)
|
||||
return m_USART3.available();//AvailUSART3();
|
||||
#elif defined(STM32F4_PI) || defined(STM32F4_F4M) || defined(STM32F722_PI) || defined(STM32F722_F7M) || defined(STM32F722_RPT_HAT) || defined(STM32F4_DVM) || defined(STM32F7_DVM) || defined(STM32F4_EDA_405) || defined(STM32F4_EDA_446)
|
||||
return m_USART1.available();//AvailUSART1();
|
||||
#elif defined(STM32F4_NUCLEO) || defined(STM32F4_RPT_HAT_TGO)
|
||||
return m_USART2.available();//AvailUSART2();
|
||||
#elif defined(DRCC_DVM)
|
||||
return m_USART1.available();//AvailUSART1();
|
||||
#endif
|
||||
|
||||
case 3U:
|
||||
#if defined(STM32F4_NUCLEO) && defined(STM32F4_NUCLEO_ARDUINO_HEADER)
|
||||
return m_USART1.available(); //AvailUSART1();
|
||||
#elif defined(DRCC_DVM)
|
||||
return m_USART2.available(); //AvailUSART2();
|
||||
#else
|
||||
return m_UART5.available();//AvailUART5();
|
||||
#endif
|
||||
|
||||
default:
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
int CSerialPort::availableForWriteInt(uint8_t n)
|
||||
{
|
||||
switch (n) {
|
||||
case 1U:
|
||||
#if defined(STM32F4_DISCOVERY) || defined(STM32F7_NUCLEO)
|
||||
return m_USART3.availableForWrite(); //AvailForWriteUSART3();
|
||||
#elif defined(STM32F4_PI) || defined(STM32F4_F4M) || defined(STM32F722_PI) || defined(STM32F722_F7M) || defined(STM32F722_RPT_HAT) || defined(STM32F4_DVM) || defined(STM32F7_DVM) || defined(STM32F4_EDA_405) || defined(STM32F4_EDA_446)
|
||||
return m_USART1.availableForWrite(); //AvailForWriteUSART1();
|
||||
#elif defined(STM32F4_NUCLEO) || defined(STM32F4_RPT_HAT_TGO)
|
||||
return m_USART2.availableForWrite();//AvailForWriteUSART2();
|
||||
#elif defined(DRCC_DVM)
|
||||
return m_USART1.availableForWrite();//AvailForWriteUSART1();
|
||||
#endif
|
||||
case 3U:
|
||||
#if defined(STM32F4_NUCLEO) && defined(STM32F4_NUCLEO_ARDUINO_HEADER)
|
||||
return m_USART1.availableForWrite(); //AvailForWriteUSART1();
|
||||
#elif defined(DRCC_DVM)
|
||||
return m_USART2.availableForWrite();//AvailForWriteUSART2();
|
||||
#else
|
||||
return m_UART5.availableForWrite();//AvailForWriteUART5();
|
||||
#endif
|
||||
default:
|
||||
return 0;
|
||||
}
|
||||
switch (n) {
|
||||
case 1U:
|
||||
#if defined(STM32F4_DISCOVERY) || defined(STM32F7_NUCLEO)
|
||||
return m_USART3.availableForWrite(); //AvailForWriteUSART3();
|
||||
#elif defined(STM32F4_PI) || defined(STM32F4_F4M) || defined(STM32F722_PI) || defined(STM32F722_F7M) || defined(STM32F722_RPT_HAT) || defined(STM32F4_DVM) || defined(STM32F7_DVM) || defined(STM32F4_EDA_405) || defined(STM32F4_EDA_446)
|
||||
return m_USART1.availableForWrite(); //AvailForWriteUSART1();
|
||||
#elif defined(STM32F4_NUCLEO) || defined(STM32F4_RPT_HAT_TGO)
|
||||
return m_USART2.availableForWrite();//AvailForWriteUSART2();
|
||||
#elif defined(DRCC_DVM)
|
||||
return m_USART1.availableForWrite();//AvailForWriteUSART1();
|
||||
#endif
|
||||
|
||||
case 3U:
|
||||
#if defined(STM32F4_NUCLEO) && defined(STM32F4_NUCLEO_ARDUINO_HEADER)
|
||||
return m_USART1.availableForWrite(); //AvailForWriteUSART1();
|
||||
#elif defined(DRCC_DVM)
|
||||
return m_USART2.availableForWrite();//AvailForWriteUSART2();
|
||||
#else
|
||||
return m_UART5.availableForWrite();//AvailForWriteUART5();
|
||||
#endif
|
||||
|
||||
default:
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
uint8_t CSerialPort::readInt(uint8_t n)
|
||||
{
|
||||
switch (n) {
|
||||
case 1U:
|
||||
#if defined(STM32F4_DISCOVERY) || defined(STM32F7_NUCLEO)
|
||||
return m_USART3.read();//ReadUSART3();
|
||||
#elif defined(STM32F4_PI) || defined(STM32F4_F4M) || defined(STM32F722_PI) || defined(STM32F722_F7M) || defined(STM32F722_RPT_HAT) || defined(STM32F4_DVM) || defined(STM32F7_DVM) || defined(STM32F4_EDA_405) || defined(STM32F4_EDA_446)
|
||||
return m_USART1.read();//ReadUSART1();
|
||||
#elif defined(STM32F4_NUCLEO) || defined(STM32F4_RPT_HAT_TGO)
|
||||
return m_USART2.read();//ReadUSART2();
|
||||
#elif defined(DRCC_DVM)
|
||||
return m_USART1.read();//ReadUSART1();
|
||||
#endif
|
||||
case 3U:
|
||||
#if defined(STM32F4_NUCLEO) && defined(STM32F4_NUCLEO_ARDUINO_HEADER)
|
||||
return m_USART1.read();//ReadUSART1();
|
||||
#elif defined(DRCC_DVM)
|
||||
return m_USART2.read();//ReadUSART2();
|
||||
#else
|
||||
return m_UART5.read();//ReadUART5();
|
||||
#endif
|
||||
default:
|
||||
return 0U;
|
||||
}
|
||||
switch (n) {
|
||||
case 1U:
|
||||
#if defined(STM32F4_DISCOVERY) || defined(STM32F7_NUCLEO)
|
||||
return m_USART3.read();//ReadUSART3();
|
||||
#elif defined(STM32F4_PI) || defined(STM32F4_F4M) || defined(STM32F722_PI) || defined(STM32F722_F7M) || defined(STM32F722_RPT_HAT) || defined(STM32F4_DVM) || defined(STM32F7_DVM) || defined(STM32F4_EDA_405) || defined(STM32F4_EDA_446)
|
||||
return m_USART1.read();//ReadUSART1();
|
||||
#elif defined(STM32F4_NUCLEO) || defined(STM32F4_RPT_HAT_TGO)
|
||||
return m_USART2.read();//ReadUSART2();
|
||||
#elif defined(DRCC_DVM)
|
||||
return m_USART1.read();//ReadUSART1();
|
||||
#endif
|
||||
|
||||
case 3U:
|
||||
#if defined(STM32F4_NUCLEO) && defined(STM32F4_NUCLEO_ARDUINO_HEADER)
|
||||
return m_USART1.read();//ReadUSART1();
|
||||
#elif defined(DRCC_DVM)
|
||||
return m_USART2.read();//ReadUSART2();
|
||||
#else
|
||||
return m_UART5.read();//ReadUART5();
|
||||
#endif
|
||||
|
||||
default:
|
||||
return 0U;
|
||||
}
|
||||
}
|
||||
|
||||
void CSerialPort::writeInt(uint8_t n, const uint8_t* data, uint16_t length, bool flush)
|
||||
{
|
||||
switch (n) {
|
||||
case 1U:
|
||||
#if defined(STM32F4_DISCOVERY) || defined(STM32F7_NUCLEO)
|
||||
m_USART3.write(data, length); //WriteUSART3(data, length);
|
||||
if (flush)
|
||||
m_USART3.flush();//TXSerialFlush3();
|
||||
#elif defined(STM32F4_PI) || defined(STM32F4_F4M) || defined(STM32F722_PI) || defined(STM32F722_F7M) || defined(STM32F722_RPT_HAT) || defined(STM32F4_DVM) || defined(STM32F7_DVM) || defined(STM32F4_EDA_405) || defined(STM32F4_EDA_446)
|
||||
m_USART1.write(data, length);//WriteUSART1(data, length);
|
||||
if (flush)
|
||||
m_USART1.flush();//TXSerialFlush1();
|
||||
#elif defined(STM32F4_NUCLEO) || defined(STM32F4_RPT_HAT_TGO)
|
||||
m_USART2.write(data, length);//WriteUSART2(data, length);
|
||||
if (flush)
|
||||
m_USART2.flush();//TXSerialFlush2();
|
||||
#elif defined(DRCC_DVM)
|
||||
m_USART1.write(data, length);//WriteUSART1(data, length);
|
||||
if (flush)
|
||||
m_USART1.flush();//TXSerialFlush1();
|
||||
#endif
|
||||
break;
|
||||
case 3U:
|
||||
#if defined(STM32F4_NUCLEO) && defined(STM32F4_NUCLEO_ARDUINO_HEADER)
|
||||
m_USART1.write(data, length); //WriteUSART1(data, length);
|
||||
if (flush)
|
||||
m_USART1.flush();
|
||||
#elif defined(DRCC_DVM)
|
||||
m_USART2.write(data, length);//WriteUSART2(data, length);
|
||||
if (flush)
|
||||
m_USART2.flush();//TXSerialFlush2();
|
||||
#else
|
||||
m_UART5.write(data, length);//WriteUART5(data, length);
|
||||
if (flush)
|
||||
m_UART5.flush();//TXSerialFlush5();
|
||||
#endif
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
switch (n) {
|
||||
case 1U:
|
||||
#if defined(STM32F4_DISCOVERY) || defined(STM32F7_NUCLEO)
|
||||
m_USART3.write(data, length); //WriteUSART3(data, length);
|
||||
if (flush)
|
||||
m_USART3.flush();//TXSerialFlush3();
|
||||
#elif defined(STM32F4_PI) || defined(STM32F4_F4M) || defined(STM32F722_PI) || defined(STM32F722_F7M) || defined(STM32F722_RPT_HAT) || defined(STM32F4_DVM) || defined(STM32F7_DVM) || defined(STM32F4_EDA_405) || defined(STM32F4_EDA_446)
|
||||
m_USART1.write(data, length);//WriteUSART1(data, length);
|
||||
if (flush)
|
||||
m_USART1.flush();//TXSerialFlush1();
|
||||
#elif defined(STM32F4_NUCLEO) || defined(STM32F4_RPT_HAT_TGO)
|
||||
m_USART2.write(data, length);//WriteUSART2(data, length);
|
||||
if (flush)
|
||||
m_USART2.flush();//TXSerialFlush2();
|
||||
#elif defined(DRCC_DVM)
|
||||
m_USART1.write(data, length);//WriteUSART1(data, length);
|
||||
if (flush)
|
||||
m_USART1.flush();//TXSerialFlush1();
|
||||
#endif
|
||||
break;
|
||||
|
||||
case 3U:
|
||||
#if defined(STM32F4_NUCLEO) && defined(STM32F4_NUCLEO_ARDUINO_HEADER)
|
||||
m_USART1.write(data, length); //WriteUSART1(data, length);
|
||||
if (flush)
|
||||
m_USART1.flush();
|
||||
#elif defined(DRCC_DVM)
|
||||
m_USART2.write(data, length);//WriteUSART2(data, length);
|
||||
if (flush)
|
||||
m_USART2.flush();//TXSerialFlush2();
|
||||
#else
|
||||
m_UART5.write(data, length);//WriteUART5(data, length);
|
||||
if (flush)
|
||||
m_UART5.flush();//TXSerialFlush5();
|
||||
#endif
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
Reference in New Issue
Block a user