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https://github.com/g4klx/MMDVM.git
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Clint Chance
a1794b44ed
handleIRQ() hardcoded USART1 when clearing the RXNE pending bit, so on boards where the repeater/display UART is not USART1 (Nucleo, Discovery, F767, UART5-based boards) the flag was cleared on the wrong peripheral. Use the m_usart member, matching the TXE handling below. Also fix flush(): it passed a flag constant to USART_GetITStatus and span while TXE was set, which returns immediately since TXE indicates the data register is already empty. Wait for the software TX FIFO to drain and then for the TC flag, which indicates the shift register has actually emptied.
104 lines
2.5 KiB
C++
104 lines
2.5 KiB
C++
/*
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* Copyright (c) 2020 by Jonathan Naylor G4KLX
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* Copyright (c) 2020 by Geoffrey Merck F4FXL - KC3FRA
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#if defined(STM32F4XX) || defined(STM32F7XX)
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#include "STMUART.h"
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CSTMUART::CSTMUART() :
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m_usart(NULL)
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{
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}
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void CSTMUART::init(USART_TypeDef* usart)
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{
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m_usart = usart;
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}
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void CSTMUART::write(const uint8_t * data, uint16_t length)
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{
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if(length == 0U || m_usart == NULL)
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return;
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m_txFifo.put(data[0]);
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USART_ITConfig(m_usart, USART_IT_TXE, ENABLE);//switch TX IRQ is on
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for(uint16_t i = 1U; i < length; i++) {
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m_txFifo.put(data[i]);
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}
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USART_ITConfig(m_usart, USART_IT_TXE, ENABLE);//make sure TX IRQ is on
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}
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uint8_t CSTMUART::read()
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{
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return m_rxFifo.get();
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}
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void CSTMUART::handleIRQ()
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{
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if(m_usart == NULL)
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return;
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if (USART_GetITStatus(m_usart, USART_IT_RXNE)) {
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if(!m_rxFifo.isFull())
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m_rxFifo.put((uint8_t) USART_ReceiveData(m_usart));
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USART_ClearITPendingBit(m_usart, USART_IT_RXNE);
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}
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if (USART_GetITStatus(m_usart, USART_IT_TXE)) {
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if(!m_txFifo.isEmpty())
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USART_SendData(m_usart, m_txFifo.get());
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USART_ClearITPendingBit(m_usart, USART_IT_TXE);
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if (m_txFifo.isEmpty()) // if there's no more data to transmit then turn off TX interrupts
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USART_ITConfig(m_usart, USART_IT_TXE, DISABLE);
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}
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}
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// Flushes the transmit shift register
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// warning: this call is blocking
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void CSTMUART::flush()
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{
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if(m_usart == NULL)
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return;
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// wait until the TX FIFO has drained
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while (!m_txFifo.isEmpty())
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;
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// wait until the TC flag shows the shift register is empty
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while (USART_GetFlagStatus(m_usart, USART_FLAG_TC) == RESET)
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;
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}
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uint16_t CSTMUART::available()
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{
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return m_rxFifo.isEmpty() ? 0U : 1U;
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}
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uint16_t CSTMUART::availableForWrite()
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{
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return m_txFifo.isFull() ? 0U : 1U;
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}
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#endif |